CPU3D.com / Intel to roll 32-nm process at IEDM / Intel to roll 32-nm process at IEDM

Intel to roll 32-nm process at IEDM

"Intel Corp. is expected to take the wraps off its new 32-nm process technology for high-performance microprocessors..."

Tags : CPU Intel 32 nm IEDM IEEE SRAM

Posted on Oct 28, 2008, 1:40 PM UTC by Aran White

Source : EE Times

Intel to roll 32-nm process at IEDM

At the upcoming 2008 IEEE International Electron Devices Meeting (IEDM), Intel Corp. is expected to take the wraps off its new 32-nm process technology for high-performance microprocessors.

According to the IEDM paper, Intel built a functional 32-nm, 291-Mbit SRAM array test chip with a 0.171-micron² cell size. The device has nearly 2 billion transistors, and an array density of 4.2-Mbit².

The test chip operated at 3.8-GHz at 1.1 Volt, according to the paper. Intel (Santa Clara, Calif.) is expected to deploy its first immersion lithography scanners at 32-nm. The 193-nm machines will be sourced from Nikon Corp. (Tokyo).

The process also makes use of a second-generation, high-k/metal gate technology, a strained channel, and nine levels of low-k interconnect dielectrics, according to a sneak preview of the paper.

The process enables the highest drive currents reported to date for 32-nm technology. NMOS saturated drive current is 1.55-mA_micron while the corresponding PMOS value is 1.21-mA_micron.

At IEDM, there are also other major papers. HRL Laboratories will describe the integration of RF CMOS and indium phosphide (InP) transistors.